As integrated circuit devices continue to shrink in size errors and failures due to sub-atomic particles have become more problematic. Particle induced errors and failures are most often attributed to alpha particles traveling through a semiconductor substrate and generating electron hole pairs. Such alpha particles may be generated by the decay of elements (e.g., uranium, thorium) or cosmic ray events, as but a few examples.
At larger geometry sizes (i.e., larger well sizes), the number of electron hole pairs generated by a particle may not be sufficient to induce error or failure. However, in smaller geometry structures, such as memory arrays, the number of generated electron hole pairs can be significant with respect to the relatively small size of wells and devices.
One approach to addressing errors resulting from particle induced events is shown in commonly owned, co-pending U.S. patent application Ser. No. 10/823,529 titled SOFT ERROR RESISTANT MEMORY CELL AND METHOD OF MANUFACTURE by Jin et al., filed Apr. 13, 2004, which describes how bit errors can be generated by particle strikes.
However, for complementary metal-oxide-semiconductor (CMOS) type circuits, a particle event can lead to more catastrophic results than loss of a bit value. In particular, a particle induced event can cause the condition known as “latch-up”. Such a problem can be of particular consequence in memory cell arrays having tightly integrated CMOS structures, such as static random access memory (SRAM) arrays.
Latch-up in CMOS devices has been studied exhaustively. In a latch-up condition, the forward biasing of a p-n junction results in a sudden, very high current draw. Because latch-up is a feedback response between two parasitic transistors, in order to remain in the latch-up state, the devices require a latch-up “holding” current to sustain the latch-up condition. FIG. 8. shows a typically CMOS structure and corresponding latch-up related parasitic devices. As would be understood from the figure, a latch-up holding current “lhold_lu” may be given by lhold_lu=IRW+IPNP+INPN+IRS.
To better understand various aspects of the invention, a typical particle induced latch-up event will now be described with reference to FIGS. 9A and 9B. FIG. 9A is a block schematic diagram of a column of memory cells. FIG. 9B is a graph illustrating current versus time in the latch-up event.
As shown in FIG. 9A, a column of memory cells 900 can include memory cells 902-0 to 902-n commonly connected to one or more bit lines 904. A particle event (a) results in the forward biasing of a p-n junction with memory cell 902-1. As shown in FIG. 9B, the particle event causes the current drawn through memory cell 902-1 to exceed a latch-up holding current lhold_lu with respect to the parasitic structures associated with memory cell 902-1. As a result, the current drawn by memory cell “lcell” surges to a maximum value Imax, dictated by the structure of the device.
From the above, it is understood that a latch-up holding current for a column of memory cells can be related to the structure of one memory cell in the column and/or a structure shared by adjacent memory cells of a column.
Conventional approaches to preventing latch-up are typically directed to reducing the parasitic resistances giving rise to latch-up. Such parasitic resistances are shown in FIG. 8 as Rpn and Rpp. A first conventional approach includes attempting to reduce Rpn or Rpp by placing/sizing a well/substrate tap (e.g., 800 or 802) to reduce the corresponding parasitic resistance. Such an approach can result in an unwanted increase in device size, as increased area will be required for each such tap. Further, such an approach can place unwanted design constraints on array layout.
A second conventional approach includes attempting to reduce Rpn by forming low resistance n-wells (804). However, such an approach can impose significant process restraints. Further, a lower well resistance can reduce performance of resulting p-channel transistors.
In light of the above, it would be desirable to arrive at some way of increasing a device resistance to latch-up that does suffer from the drawbacks of the above conventional approaches.